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FEATURES Dual 8-Bit ADCs on a Single Chip Low Power: 400 mW Typical On-Chip +2.5 V Reference and T/Hs 1 V p-p Analog Input Range Single +5 V Supply Operation +5 V or +3 V Logic Interface 120 MHz Analog Bandwidth Power-Down Mode: < 12 mW APPLICATIONS Digital Communications (QAM Demodulators) RGB & YC/Composite Video Processing Digital Data Storage Read Channels Medical Imaging Digital Instrumentation
Dual 8-Bit, 60 MSPS A/D Converter AD9059
FUNCTIONAL BLOCK DIAGRAM
VD PWRDN VDD
AD9059
AINA T/H ADCA 8 D7A-D0A
VREF ENCODE +2.5V AINB T/H ADCB 8 D7B-D0B
GND
PRODUCT DESCRIPTION
The AD9059 is a dual 8-bit monolithic analog-to-digital converter optimized for low cost, low power, small size, and ease of use. With a 60 MSPS encode rate capability and full-power analog bandwidth of 120 MHz typical, the component is ideal for applications requiring multiple ADCs with excellent dynamic performance. To minimize system cost and power dissipation, the AD9059 includes an internal +2.5 V reference and dual track-and-hold circuits. The ADC requires only a +5 V power supply and an encode clock. No external reference or driver components are required for many applications. The AD9059's single encode input is TTL/CMOS compatible and simultaneously controls both internal ADC channels. The parallel 8-bit digital outputs can be operated from +5 V or +3 V supplies. A power-down function may be exercised to bring total consumption to < 12 mW when ADC data is not required for lengthy periods of time. In power-down mode the digital outputs are driven to a high impedance state. Fabricated on an advanced BiCMOS process, the AD9059 is available in a space saving 28-lead surface mount plastic package (28 SSOP) and is specified over the industrial (-40C to +85C) temperature range. Customers desiring single channel digitization may consider the AD9057, a single 8-bit, 60 MSPS monolithic based on the AD9059 ADC core. The AD9057 is available in a 20-lead surface mount plastic package (20 SSOP) and is specified over the industrial temperature range.
PIN CONFIGURATION
AINA 1 VREF 2 PWRDN 3 VD 4 GND 5 VDD 6
28 AINB 27 GND 26 ENCODE 25 VD
AD9059
24 GND
TOP VIEW 23 VDD D7A (MSB) 7 (Not to Scale) 22 D7B (MSB) D6A 8 D5A 9 D4A 10 D3A 11 D2A 12 D1A 13 D0A (LSB) 14 21 D6B 20 D5B 19 D4B 18 D3B 17 D2B 16 D1B 15 D0B (LSB)
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD9059-SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (V
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes Gain Error1
Gain Tempco1
D
= +5 V, VDD = +3 V; external reference; ENCODE = 60 MSPS unless otherwise noted)
Temp Test Level Min AD9059BRS Typ Max 8 +25C Full +25C Full Full +25C Full
Full
Units Bits LSB LSB LSB LSB % FS % FS
ppm/C
I VI I VI VI I VI
V
-6 -8
2.0 2.5 0.75 2.0 2.5 GUARANTEED -2.5 +6 +8
70
0.75
ANALOG INPUT Input Voltage Range (Centered at +2.5 V) Input Offset Voltage Input Resistance Input Capacitance Input Bias Current Analog Bandwidth CHANNEL MATCHING (A to B) Gain Delta Input Offset Voltage Delta BANDGAP REFERENCE Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Aperture Delay (tA) Aperture Uncertainty (Jitter) Output Valid Time (tV)2 Output Propagation Delay (tPD)2 DYNAMIC PERFORMANCE Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SINAD) (with Harmonics) fIN = 10.3 MHz fIN = 76 MHz Effective Number of Bits fIN = 10.3 MHz fIN = 76 MHz Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 10.3 MHz fIN = 76 MHz 2nd Harmonic Distortion fIN = 10.3 MHz fIN = 76 MHz 3rd Harmonic Distortion fIN = 10.3 MHz fIN = 76 MHz Two-Tone Intermodulation Distortion (IMD) Channel Crosstalk Rejection Differential Phase Differential Gain
3
+25C +25C Full +25C +25C +25C +25C +25C +25C Full Full Full Full +25C +25C Full Full +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C +25C -2-
V I VI V V I V V V VI V VI IV V V IV IV V V I V I V I V I V I V V V V V
-15 -25
1.0 0 150 2 6 120 1 4
+15 +25
16
V p-p mV mV k pF A MHz % FS mV
2.4
2.5 10
2.6
V ppm/C MSPS MSPS ns ps, rms ns ns ns ns dB dB Bits Bits dB dB dBc dBc dBc dBc dBc dBc Degrees % REV. 0
60 5 2.7 5 6.6 9.5 9 9 40 44.5 43.5 7.1 6.9 46 45 -62 -54 -60 -54 -52 -50 0.8 1.0
4.0
14.2
6.35
42
-50
-46
AD9059
Parameter DIGITAL INPUTS Logic "1" Voltage Logic "0" Voltage Logic "1" Current Logic "0" Current Input Capacitance Encode Pulse Width High (tEH) Encode Pulse Width Low (tEL) DIGITAL OUTPUTS Logic "1" Voltage (VDD = +3 V) Logic "1" Voltage (VDD = +5 V) Logic "0" Voltage (VDD = +3 V or +5 V) Output Coding POWER SUPPLY VD Supply Current (VD = +5 V) VDD Supply Current (VDD = +3 V)4
Power Dissipation5, 6 Power-Down Dissipation Power Supply Rejection Ratio (PSRR)
Temp Full Full Full Full +25C +25C +25C Full Full Full
Test Level VI VI VI VI V IV IV VI IV VI
Min 2.0
AD9059BRS Typ Max
Units V V A A pF ns ns V V V
0.8 1 1 4.5 6.7 6.7 2.95 4.95 0.05 Offset Binary Code 72 13
400 6
166 166
Full Full
Full Full +25C
VI VI
VI VI I
92 15
505 12 15
mA mA
mW mW mV/V
NOTES 1 Gain error and gain temperature coefficient are based on the ADC only (with a fixed +2.5 V external reference). 2 tV and tPD are measured from the 1.5 V level of the ENCODE to the 10%/90% levels of the digital output swing. The digital output load during test is not to exceed an ac load of 10 pF or a dc current of 40 A. 3 SNR/harmonics based on an analog input voltage of -0.5 dBFS referenced to a 1.0 V full-scale input range. 4 Digital supply current based on V DD = +3 V output drive with <10 pF loading under dynamic test conditions. 5 Power dissipation is based on 60 MSPS encode and 10.3 MHz analog input dynamic test conditions (V D = +5 V 5%, VDD = +3 V 5%). 6 Typical thermal impedance for the RS style (SSOP) 28-pin package: JC = 39C/W, CA = 70C/W, JA = 109C/W. Specifications subject to change without notice.
EXPLANATION OF TEST LEVELS
ABSOLUTE MAXIMUM RATINGS*
Test Level I - 100% production tested. II - 100% production tested at +25C and sample tested at specified temperatures. III - Sample tested only. IV - Parameter is guaranteed by design and characterization testing. V - Parameter is a typical value only. VI - 100% production tested at +25C; guaranteed by design and characterization testing for industrial temperature range.
VD, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7 V Analog Inputs . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V VREF Input . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to VD + 0.5 V Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Operating Temperature . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . -65C to +150C
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ORDERING GUIDE
Model AD9059BRS AD9059/PCB
Temperature Range - 40C to +85C +25C
Package Option RS-28 Evaluation Board
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9059 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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-3-
AD9059
N N+3 N+5
PIN DESCRIPTIONS
AIN
N+1 N+2 N+4
Pin No. 1, 28 2
Name
Function
AINA, AINB Analog Inputs for ADC A and B. VREF Internal Voltage Reference (+2.5 V Typical); Bypass with 0.1 F to Ground or Overdrive with External Voltage Reference. Power-Down Function Select; Logic HIGH for Power-Down Mode (Digital Outputs Go to HighImpedance State). Analog +5 V Power Supply. Ground. Digital Output Power Supply. Nominally +3 V to +5 V. Digital Outputs of ADCA. Digital Outputs of ADCB. Encode Clock for ADCs A and B (ADCs Sample Simultaneously On the Rising Edge of ENCODE).
tA
ENCODE
tEH
tEL tV
DIGITAL OUTPUTS
N-3
N-2
N-1
N
N+1
N+2
3
PWRDN
tPD MIN tA tEH tEL tV tPD
APERTURE DELAY PULSE WIDTH HIGH PULSE WIDTH LOW OUTPUT VALID TIME OUTPUT PROP DELAY 6.7ns 6.7ns 4.0ns 6.6ns 9.5ns 14.2ns
TYP
2.7ns
MAX
166ns 166ns
4, 25 5, 24, 27 6, 23 7-14 22-15 26
VD GND VDD D7A-D0A D7B-D0B ENCODE
Figure 1. Timing Diagram
PIN CONFIGURATION
AINA 1 VREF 2 PWRDN 3 VD 4 GND 5 VDD 6
28 AINB 27 GND 26 ENCODE 25 VD
Table I. Digital Coding (VREF = +2.5 V)
Analog Input 3.0 V 2.502 V 2.498 V 2.0 V
Voltage Level Positive Full Scale Midscale + 1/2 LSB Midscale - 1/2 LSB Negative Full Scale
Digital Output 1111 1111 1000 0000 0111 1111 0000 0000
AD9059
24 GND
TOP VIEW 23 VDD D7A (MSB) 7 (Not to Scale) 22 D7B (MSB) D6A 8 D5A 9 D4A 10 D3A 11 D2A 12 D1A 13 D0A (LSB) 14 21 D6B 20 D5B 19 D4B 18 D3B 17 D2B 16 D1B 15 D0B (LSB)
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AD9059
0 -10 -20 -30 -40 ENCODE = 60MSPS ANALOG IN = 10.3MHz, -0.5dBFS SINAD = 43.9dB ENOB = 7.0 BITS SNR = 45.1dB
-30 -35 -40 -45 2ND HARMONIC dB -50 -55 ENCODE = 60MSPS AIN = -0.5dBFS
dB
-50 -60 -70 -80 -90
-60 3RD HARMONIC -65 -70
0 FREQUENCY - MHz 30
0
20
40
60
80
100
120
140
160
ANALOG INPUT FREQUENCY - MHz
Figure 2. FFT Spectral Plot 60 MSPS, 10.3 MHz
Figure 5. Harmonic Distortion vs. AIN Frequency
0 -10 -20 -30 -40 ENCODE = 60MSPS ANALOG IN = 76MHz, -0.5dBFS SINAD = 43.0dB ENOB = 6.85 BITS SNR = 44.1dB
0 -10 -20 -30 -40 ENCODE = 60MSPS F1 IN = 9.5MHz @ -7.0dBFS F2 IN = 9.9MHz @ -7.0dBFS 2F1 - F2 = -52.0dBc 2F2 - F1 = -53.0dBc
dB
-50 -60 -70 -80 -90
dB
-50 -60 -70 -80 -90
0 FREQUENCY - MHz 30
0
10 20 FREQUENCY - MHz
30
Figure 3. Spectral Plot 60 MSPS, 76 MHz
Figure 6. Two-Tone IMD
46 SNR 44 42 40 dB 38 36 34 32 30
54 AIN = 10.3MHz, -0.5dBFS 48 SNR
SINAD
42 SINAD 36
dB
80 100 120 140 160
ENCODE = 60MSPS AIN = -0.5dBFS
30 24 18 12 6 5 10 20 30 40 50 60 ENCODE RATE - MSPS 70 80 90
0
20
40
60
ANALOG INPUT FREQUENCY - MHz
Figure 4. SINAD/SNR vs. AIN Frequency
Figure 7. SINAD/SNR vs. Encode Rate
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-5-
AD9059
600 AIN = 10.3MHz, -0.5dBFS 550 10 500
POWER - mW
12 11 VDD = +3V
9.5 9.0 tPD - ns
450 400 350
VDD = +5V
8.5 8.0 7.5 VDD = +5V
300 250
VDD = +3V
7.0 6.5 6.0 -45
5
10
20
30 40 50 60 ENCODE RATE - MSPS
70
80
90
0
25 TEMPERATURE - C
70
90
Figure 8. Power Dissipation vs. Encode Rate
Figure 11. tPD vs. Temperature/Supply (+3 V/+5 V)
45.5 SNR 45.0 44.5 SINAD 44.0
dB
46 45.5 45 44.5 44
dB
SNR
43.5 43
43.5 43.0 42.5 42.0 ENCODE = 60MSPS AIN = 10.3MHz, -0.5dBFS
SINAD
42.5 42 41.5 41 ENCODE = 60MSPS AIN = 10.3MHz, -0.5dBFS
41.5 -45
0
25 TEMPERATURE - C
70
90
40.5 5.8
6.7
7.5 8.35 9.2 ENCODE HIGH PULSE WIDTH - ns
10
10.9
Figure 9. SINAD/SNR vs. Temperature
Figure 12. SINAD/SNR vs. Encode Pulse Width
0 -0.2 -0.4
GAIN ERROR - %
0 -1 -2 -3
ADC GAIN - dB
-0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -45
-4 -5 -6 -7 -8 -9 ENCODE = 60MSPS AIN = -0..5dBFS
0
25 TEMPERATURE - C
70
90
-10
1
2
100 5 10 20 50 ANALOG FREQUENCY - MHz
200
500
Figure 10. ADC Gain vs. Temperature (With External +2.5 V Reference)
Figure 13. ADC Frequency Response
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AD9059
THEORY OF OPERATION
The AD9059 combines Analog Devices' proprietary MagAmp gray code conversion circuitry with flash converter technology to provide dual high performance 8-bit ADCs in a single low cost monolithic device. The design architecture ensures low power, high speed, and 8-bit accuracy. The AD9059 provides two linked ADC channels that are clocked from a single ENCODE input (refer to block diagram). The two ADC channels simultaneously sample the analog inputs (AINA and AINB) and provide non-interleaved parallel digital outputs (D0A-D7A and D0B-D7B). The voltage reference (VREF) is internally connected to both ADCs so channel gains and offsets will track if external reference control is desired. The analog input signal is buffered at the input of each ADC channel and applied to a high speed track-and-hold. The T/H circuit holds the analog input value during the conversion process (beginning with the rising edge of the ENCODE command). The T/H's output signal passes through the gray code and flash conversion stages to generate coarse and fine digital representations of the held analog input level. Decode logic combines the multistage data and aligns the 8-bit word for strobed outputs on the rising edge of the ENCODE command. The MagAmp/Flash architecture of the AD9059 results in three pipeline delays for the output data.
USING THE AD9059 Analog Inputs
applied to the VREF pin to overdrive the internal voltage reference for gain adjustment of up to 10% (the VREF pin is internally tied directly to the ADC circuitry). ADC gain and offset will vary simultaneously with external reference adjustment with a 1:1 ratio (a 2% or 50 mV adjustment to the +2.5 V reference varies ADC gain by 2% and ADC offset by 50 mV). Theoretical input voltage range versus reference input voltage may be calculated from the following equations: VRANGE (p-p) = VREF/2.5 VMIDSCALE = VREF VTOP-OF-RANGE = VREF + VRANGE/2 VBOTTOM-OF-RANGE = VREF - VRANGE/2 The external reference should have a 1 mA minimum sink/ source current capability to ensure complete overdrive of the internal voltage reference.
Digital Logic (+5 V/+3 V Systems)
The digital inputs and outputs of the AD9059 can easily be configured to interface directly with +3 V or +5 V logic systems. The encode and power-down (PWRDN) inputs are CMOS stages with TTL thresholds of 1.5 V, making the inputs compatible with TTL, +5 V CMOS, and +3 V CMOS logic families. As with all high speed data converters, the encode signal should be clean and jitter free to prevent degradation of ADC dynamic performance. The AD9059's digital outputs will also interface directly with +5 V or +3 V CMOS logic systems. The voltage supply pins (VDD) for these CMOS stages are isolated from the analog VD voltage supply. By varying the voltage on these supply pins the digital output HIGH levels will change for +5 V or +3 V systems. The VDD pins are internally connected on the AD9059 die. Care should be taken to isolate the VDD supply voltages from the +5 V analog supply to minimize noise coupling into the ADCs. The AD9059 provides high impedance digital output operation when the ADC is driven into power-down mode (PWRDN, logic HIGH). A 200 ns (minimum) power-down time should be provided before a high impedance characteristic is required. A 200 ns power-up period should be provided to ensure accurate ADC output data after reactivation (valid output data is available three clock cycles after the 200 ns delay).
Timing
The AD9059 provides independent single-ended high impedance (150 k) analog inputs for the dual ADCs. Each input requires a dc bias current of 6 A (typical) centered near +2.5 V ( 10%). The dc bias may be provided by the user or may be derived from the ADC's internal voltage reference. Figure 14 shows a low cost dc bias implementation allowing the user to capacitively couple ac signals directly into the ADC without additional active circuitry. For best dynamic performance the VREF pin should be decoupled to ground with a 0.1 F capacitor (to minimize modulation of the reference voltage), and the bias resistor should approximately 1 k. Figure 15 shows typical connections for high performance dc biasing using the ADC's internal voltage reference. All components may be powered from a single +5 V supply (example analog input signals are referenced to ground).
Voltage Reference
A stable and accurate +2.5 V voltage reference is built into the AD9059 (VREF). The reference output is used to set the ADC gain/offset and can provide dc bias for the analog input signals. The internal reference is tied to the ADC circuitry through a 800 internal impedance and is capable of providing 300 A external drive current (for dc biasing the analog input or other user circuitry). Some applications may require greater accuracy, improved temperature performance, or gain adjustments which cannot be obtained using the internal reference. An external voltage may be
The AD9059 is guaranteed to operate with conversion rates from 5 MSPS to 60 MSPS. At 60 MSPS the ADC is designed to operate with an encode duty cycle of 50%, but performance is insensitive to moderate variations. Pulse width variations of up to 10% (allowing the encode signal to meet the minimum/ maximum HIGH/LOW specifications) will cause no degradation in ADC performance (refer to Figure 1 Timing Diagram). Due to the linked ENCODE architecture of the ADCs, the AD9059 cannot be operated in a two-channel ping-pong mode.
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AD9059
Power Dissipation
1k +5V 1k VIN A +5V
The power dissipation of the AD9059 is specified to reflect a typical application setup under the following conditions: encode is 60 MSPS, analog input is -0.5 dBFS at 10.3 MHz, VD is +5 V, VDD is +3 V, and digital outputs are loaded with 7 pF typical (10 pF maximum). The actual dissipation will vary as these conditions are modified in user applications. Figure 8 shows typical power consumption for the AD9059 versus ADC encode frequency and VDD supply voltage.
+5V
AD8041
1 10k 3 10k +5V 0.1F VREF AINA
AD9059
AD8041
1k VIN B (-0.5V TO +0.5V) 1k 28 AINB
0.1F VINA (1V p-p) 1k EXTERNAL VREF (OPTIONAL) 3 VREF 0.1F 1k VINB (1V p-p) 0.1F 28 AINB
IF IN 90
1 AINA
AD9059
Figure 15. DC Coupled AD9059 (VIN Inverted)
AD9059
BPF ADC
BPF
ADC
VCO
VCO
Figure 14. Capacitively Coupled AD9059
A power-down function allows users to reduce power dissipation when ADC data is not required. A TTL/CMOS HIGH signal (PWRDN) shuts down portions of the dual ADC and brings total power dissipation to less than 10 mW. The internal bandgap voltage reference remains active during power-down mode to minimize ADC reactivation time. If the power-down function is not desired, Pin 3 should be tied to ground. Both ADC channels are controlled simultaneously by the PWRDN pin; they cannot be shut down or turned on independently.
Applications
Figure 16. I and Q Digital Receiver
The high sampling rate and analog bandwidth of the AD9059 are ideal for computer RGB video digitizer applications. With a full-power analog bandwidth of 2x the maximum sampling rate, the ADC provides sufficient pixel-to-pixel transient settling time to ensure accurate 60 MSPS video digitization. Figure 17 shows a typical RGB video digitizer implementation for the AD9059.
AD9059
RED ADC 8
The wide analog bandwidth of the AD9059 makes it attractive for a variety of high performance receiver and encoder applications. Figure 16 shows the dual ADC in a typical low cost I & Q demodulator implementation for cable, satellite, or wireless LAN modem receivers. The excellent dynamic performance of the ADC at higher analog input frequencies and encode rates empowers users to employ direct IF sampling techniques (refer to Figure 3, Spectral Plot). IF sampling eliminates or simplifies analog mixer and filter stages to reduce total system cost and power.
GREEN
ADC
8 PIXEL CLOCK
H-SYNC
PLL 8
BLUE
ADC
ADC
AD9059
Figure 17. RGB Video Encoder
-8-
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AD9059
+VD +VD +VDD +3V TO +5V +VD
800
3k VREF ENCODE PWRDN D0-D7 AIN
500 VREF
+2.5V
2.5k
Voltage Reference
Digital Inputs
Digital Outputs
Analog Inputs
Figure 18. Equivalent Circuits
Evaluation Board
The AD9059/PCB evaluation board provides an easy-to-use analog/digital interface for the dual 8-bit, 60 MSPS ADC. The board includes typical hardware configurations for a variety of high speed digitization evaluations. On-board components include the AD9059 (in the 28-pin SSOP package), optional analog input buffer amplifiers, digital output latches, board timing drivers, and configurable jumpers for ac coupling, dc coupling, and power-down function testing. The board is configured at shipment for dc coupling using the AD9059's internal reference. For dc coupled analog input applications, amplifiers U3 and U4 are configured to operate as unity gain inverters with adjustable offset for the analog input signals. For full-scale ADC drive each analog input signal should be 1 V p-p into 50 referenced to ground. Each amplifier offsets its analog signal by +VREF (+2.5 V typical) to center the voltage for proper ADC input drive. For dc coupled operation, connect E7 to E9 (analog input A to R11), E14 to E13 (amplifier output to analog input A of AD9059), E4 to E5 (analog input B to R10), and E11 to E10 (amplifier output to analog input B of AD9059) using the board jumper connectors. For ac coupled analog input applications, amplifiers U3 and U4 are removed from the analog signal paths. The analog signals are coupled through capacitors C11 and C12, each terminated to the VREF voltage through separate 1 k resistors (providing bias current for the AD9059 analog inputs, AINA and AINB).
Analog input signals to the board should be 1 V p-p into 50 for full-scale ADC drive. For ac coupled operation, connect E7 to E8 (analog input A to C12 feedthrough capacitor), E13 to E15 (C12 to R15 termination resistor for channel A), E4 to E6 (analog input B to C11 feedthrough capacitor), and E10 to E12 (C11 to R14 termination resistor for channel B) using the board jumper connectors. The on-board reference voltage may be used to drive the ADC or an external reference may be applied. The standard configuration employs the internal voltage reference without any external connection requirements. An external voltage reference may be applied at board connector input REF to overdrive the limited current output of the AD9059's internal voltage reference. The external voltage reference should be +2.5 V typical. The power-down function of the AD9059 can be exercised through a board jumper connection. Connect E2 to E1 (+5 V to PWRDN) for power-down mode operation. For normal operation, connect E3 to E1 (ground to PWRDN). The encode signal source should be TTL/CMOS compatible and capable of driving a 50 termination. The digital outputs of the AD9059 are buffered through latches on the evaluation board (U5 and U6) and are available for the user at connector Pins 30-37 and Pins 22-29. Latch timing is derived from the ADC ENCODE clock and a digital clocking signal is provided for the board user at connector Pins 2 and 21.
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-9-
AD9059
ANALOG IN-A BNC J5 E8 E7 R13 50 E9 R11 1k J9, VDD
U4 AD8041Q
1 NC 2 3 4 -VS R7 1k R8 10k R9 10k 8 DIS 7 +5V +VS 6 5 NC R5 10
C12 0.1F C16 10F E14 E13 E15 R15 1k C17 10F J1, REF C10 0.1F C8 0.1F D7A D6A D5A D4A D3A D2A D1A D0A 1 2 3 4 5 6 7 8 9 10 11 12 13 14
U1 AD9059RS
C9 0.1F
P2 C37DRPF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
+5V
AINA REF PWRDN VD GND VDD D7A D6A D5A D4A D3A D2A D1A D0A
R14 1k
+5V
E2 E1 E3 PWRDN E12
28 AINB 27 GND 26 ENC 25 +5V VD 24 GND 23 VDD 22 D7B D7B 21 D6B D6B 20 D5B D5B 19 D4B D4B 18 D3B D3B 17 D2B D2B 16 D1B D1B 15 D0B D0B
U5 74ACQ574
D0B D1B D2B D3B D4B D5B D6B D7B 9 8 7 6 5 4 3 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q CK OE 11 1 12 13 14 15 16 17 18 19 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
R8 1k R4 10
E10 E11
U6 74ACQ574
D7A D6A D5A D4A D3A D2A D1A D0A BNC J10 1 9 8 7 6 5 4 3 2 8D 8Q 7D 7Q 6D 6Q 5D 5Q 4D 4Q 3D 3Q 2D 2Q 1D 1Q CK OE 11 1 12 13 14 15 16 17 18 19 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0
ANALOG IN-B BNC J4 E5 E4 E6 R12 50 R10 1k
U3 AD8041Q
1 NC 2 3 4 -VS 8 DIS 7 +VS +5V 6 5 NC
C11 0.1F
U7 74AC00
3
J11, VD +5V C3 0.1F C4 0.1F
C6 0.1F C5 0.1F
C7 0.1F C13 0.1F
C14 0.1F C15 10F
ENCODE R15 50
2
U7 74AC00
4 5 6
DECOUPLING CAPS J12, GND
12
U7 74AC00
11
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DA0 DA1 DA2 DA3 DA4 DA5 DA6 DA7
13
Figure 19. AD9059 Dual Evaluation Board Schematic
-10-
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AD9059
Figure 20. Evaluation Board Layout (Top)
Figure 21. Evaluation Board Layout (Bottom)
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AD9059
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead SSOP (RS-28)
0.407 (10.34) 0.397 (10.08)
28
15
0.212 (5.38)
0.301 (7.64)
1
14
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.205 (5.21)
0.311 (7.9)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.03 (0.762) 0.022 (0.558)
-12-
REV. 0
PRINTED IN U.S.A.
C2160-10-7/96

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